This invention is in the field of semiconductor processing. This invention relates generally to techniques for preparation of ultra-shallow semiconductor junctions.
The continuing trend toward smaller, higher speed microelectronic devices requires integrated circuit designs characterized by smaller feature sizes and closer spacing between electrical components. These requirements have generated an immediate demand for methods for fabricating extremely shallow and spatially well defined dopant-containing semiconductor layers that exhibit very low electrical resistance in microelectronic devices. For example, current complementary metal oxide semiconductor (CMOS) transistors in integrated microelectronic circuits require source-drain junction depths of less than 100 nanometers, and it is predicted that a further decrease of source-drain junction depths by a factor of ten will be required to continue scaling of microelectronic device performance according to Moore's Law: the doubling of the density of transistors on a chip about every 18 months. The International Technology Roadmap for Semiconductors currently acknowledges, however, that there are no known manufacturing solutions to satisfy these rapidly evolving device requirements. Accordingly, fabrication of extremely shallow dopant-containing semiconductor layers having low electrical resistance, such as dopant-containing layers comprising P-N junctions in CMOS transistors, is a fundamental barrier to continued advances in the performance of many microelectronic devices.
The fabrication of integrated electronic circuits having reduced feature sizes requires methods for introducing conductivity-altering dopant materials into semiconductor substrates that provide control of electrically active dopant concentrations in both lateral and vertical dimensions. Semiconductor dopants, such as boron, arsenic or phosphorous atoms, may be introduced into semiconductor layers of microelectronic devices by thermal diffusion methods, or by ion implantation followed by annealing. For the fabrication of high density integrated electrical circuits, however, ion implantation techniques, particularly those employing low implantation energies, are generally preferred over thermal diffusion methods because ion implantation provides reproducible and precise control over the spatial distribution of dopants implanted into the bulk phase of a semiconductor substrate. Furthermore, thermal diffusion methods are susceptible to problems associated with lateral diffusion of dopants, poor control of dopant concentrations and a propensity to generate dislocations, which can significantly impede satisfaction of the feature size and spacing requirements of electrical components in dense integrated electrical circuits. As a result of these considerations, source-drain junctions in most high density integrated circuits are currently fabricated using ion implantation methods.
In conventional ion implantation methods, a selected semiconductor dopant material is ionized in an ion source and accelerated to form an ion beam having a selected distribution of energies. The ion beam is directed to an exposed surface of a semiconductor substrate, and the accelerated ions penetrate the exposed surface and enter the bulk phase. Ions lose energy via collisions with atoms in the semiconductor substrate, thereby eventually coming to rest and becoming embedded in the substrate. The concentration of dopant implanted in the substrate may be controlled by selection of the flux of the ion beam together with the total implantation time, and the dopant depth profile in the semiconductor substrate can be controlled to some extent by selection of the acceleration energy imparted to the ion beam. After implantation, the dopant-containing layer is annealed, often to temperatures over 1000 degrees Celsius, to electrically activate the dopant atoms by positioning them into substitutional sites in the lattice of the semiconductor substrate. In addition, annealing after implantation promotes repositioning of atoms comprising the semiconductor into lattice sites, thereby repairing disruptions of the semiconductor lattice caused by dopant implantation.
The depth of dopant material in a semiconductor substrate is largely determined by the implantation energies employed during ion implantation. Shallower dopant containing layers can be prepared using lower ion implantation energies. Subsequent annealing of the dopant-containing layer, however, inevitably causes dopant atoms to diffuse, which thereby increases the physical dimensions of the dopant-containing layer. Current annealing technologies have run into a limit in their ability to simultaneously increase dopant activation and decrease dopant diffusion, especially for the key dopant boron. This problem has been worsened by the need to continually reduce processing temperatures to avoid damaging structures already in place during device fabrication.
In “soak” annealing, a semiconductor wafer is held at constant temperature for several minutes. It is sometimes used for “solid phase epitaxial regrowth” (SPER), in which a doped layer of amorphous silicon is grown and then heated with a large crystalline seed layer underneath to guide the crystal formation of the doped layer. Much research has gone into SPER, though it does not appear to be the method the semiconductor industry is moving toward. In “spike” annealing, the temperature is ramped by incandescent light heating (after a temperature stabilization step of several tens of seconds at 600-800° C.) at 25-400° C./second up to typically about 1050° C. The dwell time near the top of the spike is 0.5-1 second, and is governed by the time it takes for the lamps to cool down after power is cut (due to radiant heat loss).
There are two kinds of millisecond heating methods that the industry is moving toward. One is “flash” annealing, wherein the wafer is brought to a baseline temperature of several hundred degrees by conventional incandescent light, and then exposed to a pulse of light from a bank of flashlamps that are on for about 1 millisecond. Only a thin skin of Si near the surface of the wafer is directly heated, but the skin is thick enough to encompass the devices on the surface. After the lamps go off, rapid heat conduction from the skin into the underlying wafer rapidly cools the skin region back down on a millisecond time scale. To some extent, the heating rate can be varied by changing the timing of the electrical discharge that powers the flash. In “laser spike annealing” (LSA), a high-power continuous-wave laser is rastered across the wafer surface. The heating rate is set by the scan speed.
Both flash and laser annealing can be employed in various combinations with spike annealing, mainly because it is found empirically that the millisecond techniques do a comparatively poor job of removing implantation damage, which leads to harmful leakage currents in the final device. Up to now there has been little rational design for these recipes because the mechanisms by which millisecond annealing techniques achieve their improvements in dopant activation and diffusion (compared to spike annealing) were unknown. There have also been problems with metastability of the activated dopant in millisecond annealing; subsequent thermal steps tend to decrease the degree of dopant activation.
Dopant diffusion behavior is largely determined by a complex interplay between lone interstitials of both dopant and semiconductors, and by interstitial clusters containing various mixtures of dopant and semiconductors that render the lone interstitials immobile. Vacancies also play a role to some extent. During implantation, numerous lone interstitials are created that diffuse quickly. Some interstitials annihilate vacancies, but because the extra atoms introduced by implantation cause the interstitials to outnumber vacancies, the remaining interstitials accrete into clusters. Subsequent annealing dissociates these clusters releasing both semiconductor and dopant interstitials. Some dopant atoms enter lattice sites and become electrically activated by participating in “kick in” substitution reactions that displace atoms of the host semiconductor. However, semiconductor interstitials may reverse this process by participating in efficient “kick out” substitution reactions that convert immobilized, electrically active dopant atoms in substitutional atomic sites into highly mobile, electrically inactive dopant atoms. Such enhanced diffusion attributed to processes promoted by interstitial point defects generated during implantation or thermal processing comprise the primary portion of what are commonly referred to as transient enhanced diffusion (TED) mechanisms. These complex diffusion mechanisms constitute a fundamental limit on the control of physical dimensions of dopant-containing layers prepared by ion implantation methods and currently impede reproducible fabrication of ultra-shallow (<200 nm) dopant-containing layers.
The undesirable effects of TED are exacerbated by the higher concentrations of active dopant required for improved microelectronic device performance. Such high concentrations are well above the thermodynamic solubility limit and, thus the corresponding structures are thermodynamically unstable. Ion implantation at the high ion fluxes required to achieve such dopant concentrations creates a large number of defects and interstitials in the bulk phase of the semiconductor substrate which promotes fast TED of the dopants during annealing. These TED mechanisms involving interstitials ultimately results in significant junction deepening. In addition, implantation at high ion fluxes may generate electrically charged defect sites residing at the exposed surface of the semiconductor layer in sufficient numbers that they couple to the motion of charge defects in the underlying bulk. As bulk defects mediate diffusion of dopants in the bulk phase, such surface electrical charges can induce a corresponding change in the dopant concentration depth profile, generally deepening it. Accordingly, while ion implantation provides some degree of control of electrically active dopant concentrations and concentration depth profiles in semiconductor substrates, additional means of controlling dopant diffusion during annealing is greatly needed to reduce structure sizes and to provide improved precision of dopant depth profiles (in both vertical and lateral directions) necessary for the development of the next generation of higher performing integrated electronic devices.
A number of approaches for reducing TED in implanted semiconductor substrates have been developed over the last decade to enable fabrication of very shallow dopant-containing semiconductor layers, such as P-N junctions in CMOS transistors. Substantial research has been directed at developing methods of engineering various kinds of defects in the bulk phase of semiconductor substrates which provide an effective sink for semiconductor interstitials. These methods include the use of foreign atoms, such as carbon or halogens, dislocation loops, and co-implantation with high energy ions. Such defect engineering methods, however, have generally demonstrated limited utility. Other approaches to reducing TED in implanted semiconductor substrates include laser annealing and deposition methods for growing ultra thin dopant-containing junctions. While these methods may effectively limit the occurrence of TED, implementation of these methods is expected to require solutions to a large number of problems associated with integration of these methods into existing and well developed semiconductor processing techniques. Such integration issues remain a significant barrier to adoption of these approaches for fabricating ultra-shallow dopant-containing semiconductor layers.